How do I know where to put stitching vias?












3














I'm working on a PCB that allows me to attach a TSSOP IO expander to a breadboard more easily for experimenting. I asked a question regarding the configuration of decoupling capacitors for an IC with 2 supply pins.



One of the recommendations was to add ground pours to the top and bottom layers of the PCB to create low impedance ground connections for the decoupling capacitors and to tie the top and bottom layers with several stitching vias.



How do I know how many stitching vias to place and how do I know where to place them?



Here is what the board looks like so far:
enter image description here




Edit:



Because I'm new to electrical engineering (I'm barely at hobbyist level), it really helps me to see solutions visually. For folks finding this in the future, here's what my latest state is:



enter image description here






pcb-design decoupling-capacitor via ground-plane copper-pour







share|improve this question





























    3














    I'm working on a PCB that allows me to attach a TSSOP IO expander to a breadboard more easily for experimenting. I asked a question regarding the configuration of decoupling capacitors for an IC with 2 supply pins.



    One of the recommendations was to add ground pours to the top and bottom layers of the PCB to create low impedance ground connections for the decoupling capacitors and to tie the top and bottom layers with several stitching vias.



    How do I know how many stitching vias to place and how do I know where to place them?



    Here is what the board looks like so far:
    enter image description here




    Edit:



    Because I'm new to electrical engineering (I'm barely at hobbyist level), it really helps me to see solutions visually. For folks finding this in the future, here's what my latest state is:



    enter image description here






    pcb-design decoupling-capacitor via ground-plane copper-pour







    share|improve this question



























      3












      3








      3


      1





      I'm working on a PCB that allows me to attach a TSSOP IO expander to a breadboard more easily for experimenting. I asked a question regarding the configuration of decoupling capacitors for an IC with 2 supply pins.



      One of the recommendations was to add ground pours to the top and bottom layers of the PCB to create low impedance ground connections for the decoupling capacitors and to tie the top and bottom layers with several stitching vias.



      How do I know how many stitching vias to place and how do I know where to place them?



      Here is what the board looks like so far:
      enter image description here




      Edit:



      Because I'm new to electrical engineering (I'm barely at hobbyist level), it really helps me to see solutions visually. For folks finding this in the future, here's what my latest state is:



      enter image description here






      pcb-design decoupling-capacitor via ground-plane copper-pour







      share|improve this question















      I'm working on a PCB that allows me to attach a TSSOP IO expander to a breadboard more easily for experimenting. I asked a question regarding the configuration of decoupling capacitors for an IC with 2 supply pins.



      One of the recommendations was to add ground pours to the top and bottom layers of the PCB to create low impedance ground connections for the decoupling capacitors and to tie the top and bottom layers with several stitching vias.



      How do I know how many stitching vias to place and how do I know where to place them?



      Here is what the board looks like so far:
      enter image description here




      Edit:



      Because I'm new to electrical engineering (I'm barely at hobbyist level), it really helps me to see solutions visually. For folks finding this in the future, here's what my latest state is:



      enter image description here






      pcb-design decoupling-capacitor via ground-plane copper-pour




      pcb-design decoupling-capacitor via ground-plane copper-pour






      share|improve this question















      share|improve this question













      share|improve this question




      share|improve this question








      edited 11 hours ago

























      asked yesterday









      D. Patrick

      19229




      19229






















          3 Answers
          3






          active

          oldest

          votes


















          5














          If you flip C2 and C3 around this could be a 1-layer board. Flipping them, would also reduce parasitic inductances due to the required vias.



          But, to answer your question, for your (low-frequency) application, stitching vias serve just one purpose, to reduce the impedance for any current traveling on the planes. That directly implies that areas of the plane that have little or no current, due to being far from the current paths, don’t require any vias.



          In your case you only have 4 pads and a pin that conduct current from the plane. You just require vias near those pads and perhaps the pin (vias are much less conductive than the pin itself). Perhaps 4 vias on the capacitors, and 2 near the IC Gnd.



          Any additional vias would mostly be cosmetic, it would be hard to tease apart the effects due to reduction in impedance due to the vias from the increase in impedance due to the added holes in the planes.



          If this was a high-frequency a application (e.g., >500MHz) vias would be required near the PCB edges, to avoid unintended emissions and you would need to take into account the impedances to the plane underneath signal lines.






          share|improve this answer























          • If I flip the caps, the Vss trace will still be short enough? And the ground pour on top will be low enough inductance that I don’t need the pour on bottom at all?
            – D. Patrick
            yesterday










          • I meant Vdd trace won’t be too long.
            – D. Patrick
            yesterday






          • 1




            @D.Patrick If you flip C2 and C3 VddI2C could actually become shorter. If you are doing a double-layer board (the difference in price might be negligible) put the plane anyway. It does not hurt anything and it will provide better shielding, a negligible effect given the application, but better anyway.
            – Edgar Brown
            yesterday










          • I added an image to the end of my question that shows my attempt to implement your suggestions. Did I more or less capture what you had in mind? (I also moved a few things around because I wanted to label a some of the pins, but I don't think I changed the circuit substantially). Thanks again for your help!!
            – D. Patrick
            yesterday










          • I hate to be a pest; I very much appreciate your help. I plan to accept your answer, but first I’d like to make sure the image I added to my question accurately represents your recommendation. When you have a second, would you mind terribly taking a quick look? I just want to make sure the question is helpful to other folks new to this like me who might understand more easily with a graphic representation. Thank you again!!
            – D. Patrick
            11 hours ago



















          2














          Put 4 at each end, and a couple under the body of the chip. I don't know that there is an exact science behind it. I try to get Gnd vias near the Gnd end of the caps too. You could move C3 & C4 up a little to get Gnd vias between them and C2 and C1.






          share|improve this answer































            -1














            Just make your top gnd and the bottom vss; this way, you don't need any Vias.



            Also, why those weird trace directions at the outer traces of the chip (pin 1 and 2 on each header)?



            Also, you don't need a via in j1_12 (aka gnd), as pads go through the board and manufactured boards (boards you don't make yourself) have pads connected through the hole.






            share|improve this answer










            New contributor




            Rayan is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
            Check out our Code of Conduct.


















            • Thanks for your answer!! What’s weird? I know so little about PCB design that I can’t tell what’s weird and what’s not. :)
              – D. Patrick
              15 hours ago






            • 3




              An answer is not the place to ask the OP for clarifications ("why those ... trace directions"). Perhaps better to obtain clarifications through comments on the question itself, then post an answer when you have a clear answer to provide.
              – Anindo Ghosh
              13 hours ago










            • The funny traces in the bottom right were an effort to keep the traces from having 90 degree angles and trapping acid during production (or something like that). In the top left, it's because I can't trace pin 1 to j1 between the caps because of the ground pour and I was trying to avoid adding a trace to the bottom of the board so I kind of had to sneak it between the jumpers. Does that make sense?
              – D. Patrick
              11 hours ago











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            3 Answers
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            active

            oldest

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            3 Answers
            3






            active

            oldest

            votes









            active

            oldest

            votes






            active

            oldest

            votes









            5














            If you flip C2 and C3 around this could be a 1-layer board. Flipping them, would also reduce parasitic inductances due to the required vias.



            But, to answer your question, for your (low-frequency) application, stitching vias serve just one purpose, to reduce the impedance for any current traveling on the planes. That directly implies that areas of the plane that have little or no current, due to being far from the current paths, don’t require any vias.



            In your case you only have 4 pads and a pin that conduct current from the plane. You just require vias near those pads and perhaps the pin (vias are much less conductive than the pin itself). Perhaps 4 vias on the capacitors, and 2 near the IC Gnd.



            Any additional vias would mostly be cosmetic, it would be hard to tease apart the effects due to reduction in impedance due to the vias from the increase in impedance due to the added holes in the planes.



            If this was a high-frequency a application (e.g., >500MHz) vias would be required near the PCB edges, to avoid unintended emissions and you would need to take into account the impedances to the plane underneath signal lines.






            share|improve this answer























            • If I flip the caps, the Vss trace will still be short enough? And the ground pour on top will be low enough inductance that I don’t need the pour on bottom at all?
              – D. Patrick
              yesterday










            • I meant Vdd trace won’t be too long.
              – D. Patrick
              yesterday






            • 1




              @D.Patrick If you flip C2 and C3 VddI2C could actually become shorter. If you are doing a double-layer board (the difference in price might be negligible) put the plane anyway. It does not hurt anything and it will provide better shielding, a negligible effect given the application, but better anyway.
              – Edgar Brown
              yesterday










            • I added an image to the end of my question that shows my attempt to implement your suggestions. Did I more or less capture what you had in mind? (I also moved a few things around because I wanted to label a some of the pins, but I don't think I changed the circuit substantially). Thanks again for your help!!
              – D. Patrick
              yesterday










            • I hate to be a pest; I very much appreciate your help. I plan to accept your answer, but first I’d like to make sure the image I added to my question accurately represents your recommendation. When you have a second, would you mind terribly taking a quick look? I just want to make sure the question is helpful to other folks new to this like me who might understand more easily with a graphic representation. Thank you again!!
              – D. Patrick
              11 hours ago
















            5














            If you flip C2 and C3 around this could be a 1-layer board. Flipping them, would also reduce parasitic inductances due to the required vias.



            But, to answer your question, for your (low-frequency) application, stitching vias serve just one purpose, to reduce the impedance for any current traveling on the planes. That directly implies that areas of the plane that have little or no current, due to being far from the current paths, don’t require any vias.



            In your case you only have 4 pads and a pin that conduct current from the plane. You just require vias near those pads and perhaps the pin (vias are much less conductive than the pin itself). Perhaps 4 vias on the capacitors, and 2 near the IC Gnd.



            Any additional vias would mostly be cosmetic, it would be hard to tease apart the effects due to reduction in impedance due to the vias from the increase in impedance due to the added holes in the planes.



            If this was a high-frequency a application (e.g., >500MHz) vias would be required near the PCB edges, to avoid unintended emissions and you would need to take into account the impedances to the plane underneath signal lines.






            share|improve this answer























            • If I flip the caps, the Vss trace will still be short enough? And the ground pour on top will be low enough inductance that I don’t need the pour on bottom at all?
              – D. Patrick
              yesterday










            • I meant Vdd trace won’t be too long.
              – D. Patrick
              yesterday






            • 1




              @D.Patrick If you flip C2 and C3 VddI2C could actually become shorter. If you are doing a double-layer board (the difference in price might be negligible) put the plane anyway. It does not hurt anything and it will provide better shielding, a negligible effect given the application, but better anyway.
              – Edgar Brown
              yesterday










            • I added an image to the end of my question that shows my attempt to implement your suggestions. Did I more or less capture what you had in mind? (I also moved a few things around because I wanted to label a some of the pins, but I don't think I changed the circuit substantially). Thanks again for your help!!
              – D. Patrick
              yesterday










            • I hate to be a pest; I very much appreciate your help. I plan to accept your answer, but first I’d like to make sure the image I added to my question accurately represents your recommendation. When you have a second, would you mind terribly taking a quick look? I just want to make sure the question is helpful to other folks new to this like me who might understand more easily with a graphic representation. Thank you again!!
              – D. Patrick
              11 hours ago














            5












            5








            5






            If you flip C2 and C3 around this could be a 1-layer board. Flipping them, would also reduce parasitic inductances due to the required vias.



            But, to answer your question, for your (low-frequency) application, stitching vias serve just one purpose, to reduce the impedance for any current traveling on the planes. That directly implies that areas of the plane that have little or no current, due to being far from the current paths, don’t require any vias.



            In your case you only have 4 pads and a pin that conduct current from the plane. You just require vias near those pads and perhaps the pin (vias are much less conductive than the pin itself). Perhaps 4 vias on the capacitors, and 2 near the IC Gnd.



            Any additional vias would mostly be cosmetic, it would be hard to tease apart the effects due to reduction in impedance due to the vias from the increase in impedance due to the added holes in the planes.



            If this was a high-frequency a application (e.g., >500MHz) vias would be required near the PCB edges, to avoid unintended emissions and you would need to take into account the impedances to the plane underneath signal lines.






            share|improve this answer














            If you flip C2 and C3 around this could be a 1-layer board. Flipping them, would also reduce parasitic inductances due to the required vias.



            But, to answer your question, for your (low-frequency) application, stitching vias serve just one purpose, to reduce the impedance for any current traveling on the planes. That directly implies that areas of the plane that have little or no current, due to being far from the current paths, don’t require any vias.



            In your case you only have 4 pads and a pin that conduct current from the plane. You just require vias near those pads and perhaps the pin (vias are much less conductive than the pin itself). Perhaps 4 vias on the capacitors, and 2 near the IC Gnd.



            Any additional vias would mostly be cosmetic, it would be hard to tease apart the effects due to reduction in impedance due to the vias from the increase in impedance due to the added holes in the planes.



            If this was a high-frequency a application (e.g., >500MHz) vias would be required near the PCB edges, to avoid unintended emissions and you would need to take into account the impedances to the plane underneath signal lines.







            share|improve this answer














            share|improve this answer



            share|improve this answer








            edited yesterday

























            answered yesterday









            Edgar Brown

            3,530425




            3,530425












            • If I flip the caps, the Vss trace will still be short enough? And the ground pour on top will be low enough inductance that I don’t need the pour on bottom at all?
              – D. Patrick
              yesterday










            • I meant Vdd trace won’t be too long.
              – D. Patrick
              yesterday






            • 1




              @D.Patrick If you flip C2 and C3 VddI2C could actually become shorter. If you are doing a double-layer board (the difference in price might be negligible) put the plane anyway. It does not hurt anything and it will provide better shielding, a negligible effect given the application, but better anyway.
              – Edgar Brown
              yesterday










            • I added an image to the end of my question that shows my attempt to implement your suggestions. Did I more or less capture what you had in mind? (I also moved a few things around because I wanted to label a some of the pins, but I don't think I changed the circuit substantially). Thanks again for your help!!
              – D. Patrick
              yesterday










            • I hate to be a pest; I very much appreciate your help. I plan to accept your answer, but first I’d like to make sure the image I added to my question accurately represents your recommendation. When you have a second, would you mind terribly taking a quick look? I just want to make sure the question is helpful to other folks new to this like me who might understand more easily with a graphic representation. Thank you again!!
              – D. Patrick
              11 hours ago


















            • If I flip the caps, the Vss trace will still be short enough? And the ground pour on top will be low enough inductance that I don’t need the pour on bottom at all?
              – D. Patrick
              yesterday










            • I meant Vdd trace won’t be too long.
              – D. Patrick
              yesterday






            • 1




              @D.Patrick If you flip C2 and C3 VddI2C could actually become shorter. If you are doing a double-layer board (the difference in price might be negligible) put the plane anyway. It does not hurt anything and it will provide better shielding, a negligible effect given the application, but better anyway.
              – Edgar Brown
              yesterday










            • I added an image to the end of my question that shows my attempt to implement your suggestions. Did I more or less capture what you had in mind? (I also moved a few things around because I wanted to label a some of the pins, but I don't think I changed the circuit substantially). Thanks again for your help!!
              – D. Patrick
              yesterday










            • I hate to be a pest; I very much appreciate your help. I plan to accept your answer, but first I’d like to make sure the image I added to my question accurately represents your recommendation. When you have a second, would you mind terribly taking a quick look? I just want to make sure the question is helpful to other folks new to this like me who might understand more easily with a graphic representation. Thank you again!!
              – D. Patrick
              11 hours ago
















            If I flip the caps, the Vss trace will still be short enough? And the ground pour on top will be low enough inductance that I don’t need the pour on bottom at all?
            – D. Patrick
            yesterday




            If I flip the caps, the Vss trace will still be short enough? And the ground pour on top will be low enough inductance that I don’t need the pour on bottom at all?
            – D. Patrick
            yesterday












            I meant Vdd trace won’t be too long.
            – D. Patrick
            yesterday




            I meant Vdd trace won’t be too long.
            – D. Patrick
            yesterday




            1




            1




            @D.Patrick If you flip C2 and C3 VddI2C could actually become shorter. If you are doing a double-layer board (the difference in price might be negligible) put the plane anyway. It does not hurt anything and it will provide better shielding, a negligible effect given the application, but better anyway.
            – Edgar Brown
            yesterday




            @D.Patrick If you flip C2 and C3 VddI2C could actually become shorter. If you are doing a double-layer board (the difference in price might be negligible) put the plane anyway. It does not hurt anything and it will provide better shielding, a negligible effect given the application, but better anyway.
            – Edgar Brown
            yesterday












            I added an image to the end of my question that shows my attempt to implement your suggestions. Did I more or less capture what you had in mind? (I also moved a few things around because I wanted to label a some of the pins, but I don't think I changed the circuit substantially). Thanks again for your help!!
            – D. Patrick
            yesterday




            I added an image to the end of my question that shows my attempt to implement your suggestions. Did I more or less capture what you had in mind? (I also moved a few things around because I wanted to label a some of the pins, but I don't think I changed the circuit substantially). Thanks again for your help!!
            – D. Patrick
            yesterday












            I hate to be a pest; I very much appreciate your help. I plan to accept your answer, but first I’d like to make sure the image I added to my question accurately represents your recommendation. When you have a second, would you mind terribly taking a quick look? I just want to make sure the question is helpful to other folks new to this like me who might understand more easily with a graphic representation. Thank you again!!
            – D. Patrick
            11 hours ago




            I hate to be a pest; I very much appreciate your help. I plan to accept your answer, but first I’d like to make sure the image I added to my question accurately represents your recommendation. When you have a second, would you mind terribly taking a quick look? I just want to make sure the question is helpful to other folks new to this like me who might understand more easily with a graphic representation. Thank you again!!
            – D. Patrick
            11 hours ago













            2














            Put 4 at each end, and a couple under the body of the chip. I don't know that there is an exact science behind it. I try to get Gnd vias near the Gnd end of the caps too. You could move C3 & C4 up a little to get Gnd vias between them and C2 and C1.






            share|improve this answer




























              2














              Put 4 at each end, and a couple under the body of the chip. I don't know that there is an exact science behind it. I try to get Gnd vias near the Gnd end of the caps too. You could move C3 & C4 up a little to get Gnd vias between them and C2 and C1.






              share|improve this answer


























                2












                2








                2






                Put 4 at each end, and a couple under the body of the chip. I don't know that there is an exact science behind it. I try to get Gnd vias near the Gnd end of the caps too. You could move C3 & C4 up a little to get Gnd vias between them and C2 and C1.






                share|improve this answer














                Put 4 at each end, and a couple under the body of the chip. I don't know that there is an exact science behind it. I try to get Gnd vias near the Gnd end of the caps too. You could move C3 & C4 up a little to get Gnd vias between them and C2 and C1.







                share|improve this answer














                share|improve this answer



                share|improve this answer








                edited 12 hours ago









                Dave Tweed♦

                118k9145256




                118k9145256










                answered yesterday









                CrossRoads

                1,2028




                1,2028























                    -1














                    Just make your top gnd and the bottom vss; this way, you don't need any Vias.



                    Also, why those weird trace directions at the outer traces of the chip (pin 1 and 2 on each header)?



                    Also, you don't need a via in j1_12 (aka gnd), as pads go through the board and manufactured boards (boards you don't make yourself) have pads connected through the hole.






                    share|improve this answer










                    New contributor




                    Rayan is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
                    Check out our Code of Conduct.


















                    • Thanks for your answer!! What’s weird? I know so little about PCB design that I can’t tell what’s weird and what’s not. :)
                      – D. Patrick
                      15 hours ago






                    • 3




                      An answer is not the place to ask the OP for clarifications ("why those ... trace directions"). Perhaps better to obtain clarifications through comments on the question itself, then post an answer when you have a clear answer to provide.
                      – Anindo Ghosh
                      13 hours ago










                    • The funny traces in the bottom right were an effort to keep the traces from having 90 degree angles and trapping acid during production (or something like that). In the top left, it's because I can't trace pin 1 to j1 between the caps because of the ground pour and I was trying to avoid adding a trace to the bottom of the board so I kind of had to sneak it between the jumpers. Does that make sense?
                      – D. Patrick
                      11 hours ago
















                    -1














                    Just make your top gnd and the bottom vss; this way, you don't need any Vias.



                    Also, why those weird trace directions at the outer traces of the chip (pin 1 and 2 on each header)?



                    Also, you don't need a via in j1_12 (aka gnd), as pads go through the board and manufactured boards (boards you don't make yourself) have pads connected through the hole.






                    share|improve this answer










                    New contributor




                    Rayan is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
                    Check out our Code of Conduct.


















                    • Thanks for your answer!! What’s weird? I know so little about PCB design that I can’t tell what’s weird and what’s not. :)
                      – D. Patrick
                      15 hours ago






                    • 3




                      An answer is not the place to ask the OP for clarifications ("why those ... trace directions"). Perhaps better to obtain clarifications through comments on the question itself, then post an answer when you have a clear answer to provide.
                      – Anindo Ghosh
                      13 hours ago










                    • The funny traces in the bottom right were an effort to keep the traces from having 90 degree angles and trapping acid during production (or something like that). In the top left, it's because I can't trace pin 1 to j1 between the caps because of the ground pour and I was trying to avoid adding a trace to the bottom of the board so I kind of had to sneak it between the jumpers. Does that make sense?
                      – D. Patrick
                      11 hours ago














                    -1












                    -1








                    -1






                    Just make your top gnd and the bottom vss; this way, you don't need any Vias.



                    Also, why those weird trace directions at the outer traces of the chip (pin 1 and 2 on each header)?



                    Also, you don't need a via in j1_12 (aka gnd), as pads go through the board and manufactured boards (boards you don't make yourself) have pads connected through the hole.






                    share|improve this answer










                    New contributor




                    Rayan is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
                    Check out our Code of Conduct.









                    Just make your top gnd and the bottom vss; this way, you don't need any Vias.



                    Also, why those weird trace directions at the outer traces of the chip (pin 1 and 2 on each header)?



                    Also, you don't need a via in j1_12 (aka gnd), as pads go through the board and manufactured boards (boards you don't make yourself) have pads connected through the hole.







                    share|improve this answer










                    New contributor




                    Rayan is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
                    Check out our Code of Conduct.









                    share|improve this answer



                    share|improve this answer








                    edited 12 hours ago









                    Dave Tweed♦

                    118k9145256




                    118k9145256






                    New contributor




                    Rayan is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
                    Check out our Code of Conduct.









                    answered 15 hours ago









                    Rayan

                    71




                    71




                    New contributor




                    Rayan is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
                    Check out our Code of Conduct.





                    New contributor





                    Rayan is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
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                    Rayan is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
                    Check out our Code of Conduct.












                    • Thanks for your answer!! What’s weird? I know so little about PCB design that I can’t tell what’s weird and what’s not. :)
                      – D. Patrick
                      15 hours ago






                    • 3




                      An answer is not the place to ask the OP for clarifications ("why those ... trace directions"). Perhaps better to obtain clarifications through comments on the question itself, then post an answer when you have a clear answer to provide.
                      – Anindo Ghosh
                      13 hours ago










                    • The funny traces in the bottom right were an effort to keep the traces from having 90 degree angles and trapping acid during production (or something like that). In the top left, it's because I can't trace pin 1 to j1 between the caps because of the ground pour and I was trying to avoid adding a trace to the bottom of the board so I kind of had to sneak it between the jumpers. Does that make sense?
                      – D. Patrick
                      11 hours ago


















                    • Thanks for your answer!! What’s weird? I know so little about PCB design that I can’t tell what’s weird and what’s not. :)
                      – D. Patrick
                      15 hours ago






                    • 3




                      An answer is not the place to ask the OP for clarifications ("why those ... trace directions"). Perhaps better to obtain clarifications through comments on the question itself, then post an answer when you have a clear answer to provide.
                      – Anindo Ghosh
                      13 hours ago










                    • The funny traces in the bottom right were an effort to keep the traces from having 90 degree angles and trapping acid during production (or something like that). In the top left, it's because I can't trace pin 1 to j1 between the caps because of the ground pour and I was trying to avoid adding a trace to the bottom of the board so I kind of had to sneak it between the jumpers. Does that make sense?
                      – D. Patrick
                      11 hours ago
















                    Thanks for your answer!! What’s weird? I know so little about PCB design that I can’t tell what’s weird and what’s not. :)
                    – D. Patrick
                    15 hours ago




                    Thanks for your answer!! What’s weird? I know so little about PCB design that I can’t tell what’s weird and what’s not. :)
                    – D. Patrick
                    15 hours ago




                    3




                    3




                    An answer is not the place to ask the OP for clarifications ("why those ... trace directions"). Perhaps better to obtain clarifications through comments on the question itself, then post an answer when you have a clear answer to provide.
                    – Anindo Ghosh
                    13 hours ago




                    An answer is not the place to ask the OP for clarifications ("why those ... trace directions"). Perhaps better to obtain clarifications through comments on the question itself, then post an answer when you have a clear answer to provide.
                    – Anindo Ghosh
                    13 hours ago












                    The funny traces in the bottom right were an effort to keep the traces from having 90 degree angles and trapping acid during production (or something like that). In the top left, it's because I can't trace pin 1 to j1 between the caps because of the ground pour and I was trying to avoid adding a trace to the bottom of the board so I kind of had to sneak it between the jumpers. Does that make sense?
                    – D. Patrick
                    11 hours ago




                    The funny traces in the bottom right were an effort to keep the traces from having 90 degree angles and trapping acid during production (or something like that). In the top left, it's because I can't trace pin 1 to j1 between the caps because of the ground pour and I was trying to avoid adding a trace to the bottom of the board so I kind of had to sneak it between the jumpers. Does that make sense?
                    – D. Patrick
                    11 hours ago


















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